For simplicity of description, the following description will be in terms of phase-locked loops in particular, but the invention can be applied to closed-loop control systems in general.
A typical phase-locked loop is shown in FIG. 1. A locally generated signal Φout is generated by a voltage-controlled oscillator or voltage-controlled multivibrator 1, whose output signal may, depending on the use to which the phase locked loop is to be put, be reduced in frequency by a programmable counter 2. As an alternative to a voltage-controlled oscillator, a current-controlled oscillator, such as a YIG oscillator, can be employed, but the present description will assume a voltage-controlled oscillator. The reduced-frequency, locally generated signal is then compared in phase with an input signal Φin by a phase comparator 3. Suitable phase comparators are well-known in the art, the Motorola MC4044 being an early example, some others being described by Peter Alfke, ‘Frequency/Phase Comparator of Phase-Locked Loops’, Xilinx Application Note XAPP 028, Dec. 2, 1996. If the locally generated signal leads the input signal in phase, the phase comparator produces, at one output, a series of pulses Φ+ whose pulse width is proportional to the phase difference. If the locally generated signal lags behind the input signal in phase, the phase comparator produces, at another output, a series of pulses Φ− whose pulse width is proportional to the phase difference. The outputs of the phase comparator are applied to a loop filter, which converts the pulse signals to a control voltage Vc, which is applied as control input to the voltage-controlled oscillator 1.
Although in FIG. 1 the locally generated signal Φout is shown as the output of the phase-locked loop, for some applications, such as FM demodulation, it may be the control voltage Vc which is the desired output.
The loop filter 4 is designed to provide the circuit as a whole with the desired operating characteristics, given the characteristics of the other components.
The principle of the design of such phase-locked loops is well-known. See, for example, Garth Nash, ‘Phase-Locked Loop Design Fundamentals’, Motorola Semiconductor Application Note AN535 (http://e-www.motorola.com/files/rf—if/doc/app—note/AN535.pdf).
A problem with phase-locked loops is that the loop gain needs to be high to ensure that the system quickly locks on to the input signal (i.e. so that the settling time is short), but if it is too high the system will be too sensitive to noise and short-term variations in the input signal. Therefore, the best loop gain for a phase-locked loop represents a compromise between a short settling time and proper operation once the loop has settled. Ideally, a phase-locked loop would start with a high loop gain during the settling time and the gain would then be reduced.